Details

<p>Introduction.- Building Blocks.- General Data-Path Circuit-Level / Design Methods.- Memories & I/O.- System-Level.- Synergistic compiler and programming languages.- Conclusion.</p>

<p>Sherief Reda is an Associate Professor (with tenure) at the School of Engineering, Brown University. He joined the Computer Engineering group at Brown in 2006 after receiving his Ph.D. in computer science and engineering from University of California, San Diego. His research interests are in the area of computer engineering, with focus on energy efficient computing systems, design automation and test of integrated circuits, and reconfigurable computing. Prof. Reda has over 85 refereed conference and journal papers (Google scholar profile). He served as a member of technical program committees for many IEEE/ACM conferences including DAC, ICCAD, ASPDAC, DATE, ICCD, GLSVLSI, and SLIP. Professor Reda received a number of awards and acknowledgments, including a hot article in Operations Research letters in 2004, a first place award in ISPD VLSI placement contest in 2005, five best paper nominations (DATE 2002, ICCAD 2005, ASPDAC 2008, ISLPED 2010 and ICCAD 2015), two best paper awards (DATE 2002 and ISLPED 2010), Brown's Salomon award in 2008, and a&nbsp;NSF CAREER award. His research has been funded by NSF, DoD ARL, DARPA, AMD, Samsung, Intel, Qualcomm and Videology. He is a senior member of IEEE.</p><p>Muhammad Shafique is&nbsp;professor at the Institute of Computer Engineering, Department of Informatics, Vienna University of Technology (TU Wien), Austria. He is directing the Group on Computer Architecture and Robust, Energy-Efficient Technologies (CARE-Tech). He received his Ph.D. in Computer Science from Karlsruhe Institute of Technology (KIT), Germany in Jan.2011. Before, he worked at Streaming Networks Pvt. Ltd. on advanced video coding systems for several years. His research interests are in computer architecture, power- and energy-efficient systems, robust computing, hardware security, neuromorphic computing, machine learning, approximate computing, neurosciences, emerging technologies, self-learning, cognitive systems, FPGAs, MPSoCs, and embedded systems. Hisresearch has a special focus on cross-layer analysis, modeling, design, and optimization of computing and memory systems covering various layers of the hardware and software stacks, as well as their integration in application use cases from Internet-of-Things (IoT), Cyber-Physical Systems (CPS), and ICT for Development (ICT4D) domains. He&nbsp;received the prestigious 2015 ACM/SIGDA Outstanding New Faculty Award, six gold medals in educational career, and several best paper awards and nominations at prestigious conferences like DATE, DAC, ICCAD and CODES+ISSS, Best Master Thesis Award, and Best Lecturer Award. He has given several Invited Talks, Tutorials, and Keynotes. He has also organized many special sessions at premier venues (like DAC, ICCAD, DATE, IOLTS, and ESWeek) and served as the TPC-chair, Track-chair, TPC-member of several premier conferences. He is a senior member of the IEEE and IEEE Signal Processing Society (SPS), and a member of ACM, SIGARCH, SIGDA, SIGBED, and HiPEAC. He holds one US patent and over 180 papers in premier journals and conferences.</p><p></p>

<p>This book provides readers with a comprehensive, state-of-the-art overview of approximate computing, enabling the design trade-off of accuracy for achieving better power/performance efficiencies, through the simplification of underlying computing resources.&nbsp; The authors describe in detail various efforts to generate approximate hardware systems, while still providing an overview of support techniques at other computing layers. The book is organized by techniques for various hardware components, from basic building blocks to general circuits and systems.</p><p><br></p><p><br></p>

<ul><li>Presents an overview of the approximate arithmetic building blocks that can be used for designing power/performance efficient computing units;</li> <li>Discusses effective memory approximation techniques to employ in conventional, i.e., DRAM and SRAM, as well as emerging, i.e., PCM and STT-RAM, memory technologies, for improving performance, power, and/or energy efficiency of the memory for error resilient applications;</li> <li>Includes an overview of hardware or software/hardware approximation techniques that operate across entire computing devices, including processors, graphical processors, and accelerators that can form a SoC with processors.</li> </ul>

Presents an overview of the approximate arithmetic building blocks that can be used for designing power/performance efficient computing units Discusses effective memory approximation techniques to employ in conventional, i.e., DRAM and SRAM, as well as emerging, i.e., PCM and STT-RAM, memory technologies, for improving performance, power, and/or energy efficiency of the memory for error resilient applications Includes an overview of hardware or software/hardware approximation techniques that operate across entire computing devices, including processors, graphical processors, and accelerators that can form a SoC with processors